1. Field of the Invention
The present invention relates to the process of designing an integrated circuit. More specifically the present invention relates to a method and an apparatus that uses Boolean expressions to represent shapes within a layout of an integrated circuit.
2. Related Art
As rapid advances in semiconductor technology make it possible to incorporate larger amounts of circuitry onto a semiconductor chip, it is becoming increasingly more difficult to generate a layout for circuit components on the semiconductor chip. This difficulty is exacerbated by differences between representations of the logical design of the circuitry and the physical layout of the circuitry.
The process of creating an integrated circuit typically starts with a logical description of the circuit. This logical description is subsequently transformed into a register transfer language (RTL) description. This RTL description is further transformed into a gate-level description of the circuit. Collectively, these steps are referred to as the xe2x80x9clogical designxe2x80x9d of the integrated circuit.
Upon completion of the logical design, the logical design is transformed into a physical design. Note that there exists a disparity between representations used in the logical design and the physical design. The logical design is typically represented in the Boolean domain, while the physical design is typically represented in the real-value domain. These different representations make the process of converting the logical design into the physical design difficult and time-consuming. Moreover, operations on the physical design involve numerical operations on real values. These numerical operations are much slower than the logical operations involving logical values that take place during the logical design process.
What is needed is a method and an apparatus that facilitates performing operations on the physical design of an integrated circuit without the problems described above.
One embodiment of the present invention provides a system that facilitates representing a shape within a layout of an integrated circuit using a Boolean expression. The system operates by first receiving a representation of the shape and then converting the representation of the shape into a Boolean expression that is formed using a Boolean coordinate system expressed in a two-dimensional Gray code. The system then performs operations on the shape by performing Boolean operations on the Boolean expression for the shape.
In one embodiment of the present invention, the system incorporates the shape into the layout of the integrated circuit by incorporating the Boolean expression for the shape into a Boolean expression for the layout.
In one embodiment of the present invention, the system expresses multiple layers on a physical chip layout by using additional bits in the two-dimensional Gray code.
In one embodiment of the present invention, the system creates a Boolean function using the Boolean expression, whereby the Boolean function can be used to determine if a point is inside the shape.
In one embodiment of the present invention, performing operations on the shape can include performing AND operations, OR operations, EXCLUSIVE-OR operations, CONTAINMENT operations, or EQUIVALENCE operations.
In one embodiment of the present invention, the system defines a non-rectangular area by combining Boolean expressions of rectangular areas.
In one embodiment of the present invention, if the shape is a rectangle, the shape is represented using coordinates for each corner of the rectangle.
In one embodiment of the present invention, if the shape has a constant width, the shape is represented using coordinates for each end of the shape.